Silicon on Insulator

Silicon on Insulator (SOI) is a technology that bonds an active wafer to a handle wafer with an oxide layer in between.

car-wireframeSQI offers a wide range of SOI products, suitable for a variety of applications.

Silicon on Insulator is commonly used in MEMS, Automotive and applications where high temperature tolerance and high noise immunity are key requirements.

Silicon on Insulator wafers are composed of a three layer material stack: Active layer of prime quality silicon (DEVICE LAYER) over a buried layer(BOX) of electrically insulating silicon dioxide, over a bulk silicon support wafer (HANDLE).

 

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SOI Wafer Specifications

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Thick Film SOI

LayerSpecification4"5"6"8"
Device wafer TypeP, NP, NP, NP, N
Device wafer Resistivity0.001~10000ohm-cm0.001~10000ohm-cm0.001~10000ohm-cm0.001~10000ohm-cm
Device wafer Orientation<100>,<110>,<111><100>,<110>,<111><100>,<110>,<111><100>,<110>,<111>
Device wafer Thickness >2.0 µ >2.0 µ >2.0µ >2.0 µ
Device wafer Tolerance+/- 0.5 µ+/- .5 µ+/- 0.5 µ+/- 0.3 µ
BOX Thickness0.1~20.0 µ0.1~20.0µ0.1~20.0µ0.1~20.0µ
BOX Uniformity+/-5%+/-5%+/-5%+/-5%
HandleTypeP, NP, NP, NP, N
HandleResistivity0.005~10000 W .cm0.005~10000 W .cm0.005~10000 W .cm0.005~10000 W .cm
HandleOrientation<100>,<110>,<111><100>,<110>,<111><100>,<110>,<111><100>,<110>,<111>
HandleThickness200~1000µ200~1000 µ200~1000 µ250~1000µ
HandleTolerance+/- 2 µ+/-2 µ+/- 3 µ+/- 3 µ

Thin Film SOI

LayerSpecification4"5"6"
Device wafer TypeP, NP, NP, N
Device wafer Resistivity1~100ohm-cm1~100ohm-cm1~100ohm-cm
Device wafer Orientation<100><100><100>
Device wafer Thickness 0.15~0.7µ0.15~0.7 µ0.15~0.7µ
Device wafer Tolerance+/- 5% µ+/- 5% µ+/- 5%µ
BOX Thickness0.1~20.0 µ0.1~20.0 µ0.1~20.0 µ
BOX Uniformity+/-5%+/-5%+/-5%
Handle wafer TypeP, NP, NP, N
Handle wafer Resistivity1~100ohm-cm1~100ohm-cm1~100ohm-cm
Handle wafer Orientation<100>,<110><100>,<110><100>,<110>
Handle wafer Thickness200~1000 µ200~1000 µ200~1000 µ
Handle wafer Tolerance+/- 2 µ+/-2 µ+/- 3 µ

Ultra Uniform SOI

LayerSpecification4"5"6"8"
Device wafer TypeP, NP, NP, NP, N
Device wafer Resistivity0.01~100ohm-cm0.01~100ohm-cm0.01~100ohm-cm0.01~100ohm-cm
Device wafer Orientation<100>,<110><100>,<110><100>,<110><100>,<110>
Device wafer Thickness0.5-10.0µ0.5-10.0 µ0.5-10.0 µ0.5-10.0 µ
Device wafer Tolerance+/- 0.15 µ+/- 0.15 µ+/- 0.15µ+/- 0.15µ
BOX Thickness0.1~20.0 µ0.1~20.0 µ0.1~20.0 µ0.1~20.0 µ
BOX Uniformity+/-5%+/-5%+/-5%+/-5%
Handle wafer TypeP, NP, NP, NP, N
Handle wafer Resistivity0.01~100ohm-cm0.01~100ohm-cm0.01~100ohm-cm0.01~100ohm-cm
Handle wafer Orientation<100>,<110><100>,<110><100>,<110><100>,<110>
Handle wafer Thickness200~1000 µ200~1000 µ200~1000 µ250~1000 µ
Handle wafer Tolerance+/- 2 µ+/-2 µ+/- 3 µ+/- 3 µ

Patterened SOI

LayerSpecification4"5"6"8"
Device wafer TypeP, NP, NP, NP, N
Device wafer Resistivity0.001~10000ohm-cm0.001~10000ohm-cm0.001~10000ohm-cm0.001~10000ohm-cm
Device wafer Orientation<100>,<110>,<111><100>,<110>,<111><100>,<110>,<111><100>,<110>,<111>
Device wafer Thickness 0.5µ0.5 µ 0.5 µ 0.5µ
Device wafer Tolerance+/- 0.5 µ+/- .5 µ+/- 0.5 µ+/- 0.3 µ
BOX Thickness0.1~20.0 µ0.1~20.0µ0.1~20.0µ0.1~20.0µ
BOX Uniformity+/-5%+/-5%+/-5%+/-5%
Handle wafer TypeP, NP, NP, NP, N
Handle wafer Resistivity0.005~10000 W .cm0.005~10000 W .cm0.005~10000 W .cm0.005~10000 W .cm
Handle wafer Orientation<100>,<110>,<111><100>,<110>,<111><100>,<110>,<111><100>,<110>,<111>
Handle wafer Thickness200~1000µ200~1000 µ200~1000 µ250~1000µ
Handle wafer Tolerance+/- 2 µ+/-2 µ+/- 3 µ+/- 3 µ